The present invention relates to a method of forming fine patterns of a semiconductor device, and more particularly, to a method of forming fine patterns of a semiconductor device, by which fine patterns are repeatedly formed at intervals of a fine pitch by using a double patterning process, thereby overcoming a resolution limit of existing exposure equipment.
Forming fine patterns is essential in manufacturing highly-integrated semiconductor devices. In order to integrate many elements within a small area, the size of the individual elements needs to be minimized. In order to form small elements, a pitch corresponding to a sum of the width of each pattern to be formed and an interval between adjacent patterns should be designed to be small. With the recent rapid reduction in design rules of semiconductor devices, there is a limit in forming desired fine-pitch patterns due to a resolution limit in photolithography for forming patterns required to manufacture semiconductor devices. In particular, in a photolithographic process for forming line and space patterns on a substrate, there is a limit in forming desired fine-pitch patterns due to a resolution limit.
In order to overcome the resolution limits in such photolithographic processes, some methods of forming fine hard mask patterns having fine pitches by using a double patterning process have been proposed. However, according to these methods of forming fine mask patterns by using the double patterning process, a material used to form the fine mask patterns needs to be deposited within an aperture having a high aspect ratio according to a deposition process such as chemical vapor deposition (CVD). Therefore, there is a limit in forming a film having good burying characteristics, namely, having no defects such as voids, within the aperture.